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4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7M1024
FEATURES:
* High-density 4K x 36 Synchronous Dual-Port SRAM module * Architecture based on Dual-Port RAM cells -- Allows full simultaneous access from both ports * Synchronous operation -- 4ns set-up to clock, 1ns hold on all control, data, and address inputs -- Data input, address, and control registers -- Fast 20ns clock to data out -- Self-timed write allows fast write cycle * Clock enable feature * Single 5V (10%) power supply * Multiple GND pins and decoupling capacitors for maximum noise immunity * Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7M1024 is a 4K x 36 bit high-speed synchronous Dual-Port Static RAM module constructed on a co-fired ce-
ramic substrate using four IDT7099 (4K x 9) Dual-Port RAMs. The IDT7M1024 module is designed to be used as a standalone 36-bit Dual-Port Static RAM. The IDT7M1024 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is independent of the HIGH and LOW periods of the clock. This allows the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. The data inputs are gated to control on-chip noise in bussed applications. The user must guarantee that the R/W pins are LOW for at least one clock cycle before any write is attempted. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. The IDT7M1024 module is packaged in a 142-lead ceramic
FUNCTIONAL BLOCK DIAGRAM
L_CLK L_CLKENL L_CEL L_OEL L_A0 - 11 L_I/O0 - 8 L_ R/W0 IDT7099 4K x 9 R_CLK R_CLKENL R_CEL R_OEL R_A0 - 11 R_I/O0 - 8 R_ R/W0
L_I/O9 - 17 IDT7099 4K x 9 L_ R/W1 L_CEH L_OEH L_I/O18 - 26 IDT7099 4K x 9 L_ R/W2 L_CLKENH L_I/O27 - 35 IDT7099 4K x 9 L_ R/W3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
R_I/O9 - 17 R_ R/W1 R_CEH R_OEH R_I/O18 - 26 R_ R/W2 R_CLKENH R_I/O27 - 35
R_ R/W3
2809 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
MARCH 1996
DSC-2809/6
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IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PGA (Pin Grid Array). All IDT military modules are constructed with semiconductor components manufactured in compliance with the latest revision of MIL-STD-883, Class B making them ideally suited to applications demanding the highest level of performance and reliability.
PIN CONFIGURATION
1 A B C D E F G H J K L M N GND L_I/O4 L_I/O8 L_I/O9 L_I/O12 L_I/O13 GND L_I/O14 L_I/O15 L_I/O20 L_I/O21 L_I/O23 GND 2 L_I/O3 L_I/O5 VCC L_I/O10 L_CE L L_OE L L_R/W0 L_R/W2 L_I/O16 L_I/O19 VCC L_I/O24 L_I/O26 3 L_I/O2 L_I/O6 L_I/O7 L_I/O11 L_CE H L_OE H L_R/W1 L_R/W3 L_I/O17 L_I/O18 L_I/O22 L_I/O25 L_I/O27 4 GND L_A2 GND L_A3 L_A4 L_A5 GND L_A6 L_A7 GND L_A8 L_I/O29 L_I/O28 L_A10 L_A9 L_I/O30 GND L_A11 L_I/O31 L_I/O32 L_I/O33 GND R_I/O35 L_I/O35 L_I/O34 R_A11 R_I/O34 R_I/O33 R_I/O32 R_A10 R_I/O30 R_I/O31 5 L_I/O1 L_A1 6 L_I/O0 L_A0 7 GND L_CLK R_CLK 8 R_I/O0 R_A0 9 R_I/O1 R_A1 10 GND R_A2 GND R_A4 R_A5 R_A6 GND R_A7 R_A8 GND R_A9 R_I/O29 R_I/O28 11 R_I/O2 R_I/O6 R_I/O7 R_I/O11 R_CE H R_OE H R_R/W1 R_R/W3 R_I/O17 R_I/O18 R_I/O22 R_I/O25 R_I/O27 12 R_I/O3 R_I/O5 VCC R_I/O10 R_CE L R_OE L R_R/W0 R_R/W2 R_I/O16 R_I/O19 VCC R_I/O24 R_I/O26 13 GND R_I/O4 R_I/O8 R_I/O9 R_I/O12 R_I/O13 GND R_I/O14 R_I/O15 R_I/O20 R_I/O21 R_I/O23 GND
2809 drw 02
L_CLKEN L
L_CLKEN H
R_CLKEN H R_CLKEN L
GND
GND
R_A3
GND
PIN NAMES
Left Port L_R/W 0-3 L_OE L, H L_CE L, H L_CLKEN L, H L_CLK L_A 0-11 L_I/O 0-35 VCC GND Right Port R_R/W 0-3 R_OE L, H R_CE L, H R_CLKEN L, H R_CLK R_A 0-11 R_I/O 0-35 Names Byte Read/Write Enables Word Output Enables Word Chip Enables Word Clock Enables Clock Inputs Address Inputs Data Input/Outputs Power Ground
2809 tbl 01
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IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Terminal Voltage Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial Military Unit V -0.5 to +7.0 -0.5 to +7.0
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Ambient Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
2809 tbl 03
VTERM(3) TA TBIAS TSTG IOUT
-0.5 to VCC 0 to +70
-0.5 to VCC
V
-55 to +125 C
Commercial
-55 to +125 -65 to +135 C -55 to +125 -65 to +150 C 50 50 mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input HIGH Voltage Input LOW Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0 -- --
Max. 5.5 0 6.0 0.8
Unit V V V V
2809 tbl 04
NOTES: 2809 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Inputs and Vcc terminals only.
NOTE: 1. VIL = -3.0V for pulse width less than 20ns.
CAPACITANCE (TA = +25C, F = 1.0MHZ)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Condition VIN = 0V VOUT = 0V Max. Unit 50 15 pF pF
2809 tbl 05
TRUTH TABLES TRUTH TABLE I: READ/WRITE CONTROL (1)
Inputs Synchronous Clk Asynchronous R/W W h l l h h Outputs I/O0-35 High-Z DATAIN DATAIN DATAOUT High-Z Mode Deselected, Power Down, Data I/O Disabled Deselected, Power Down, Data Input Enabled Write Read Data I/O Disabled
2809 tbl 06
u u u u u
CE
h h l l l
OE
X X X L H
TRUTH TABLE II: CLOCK ENABLE FUNCTION TABLE (1)
Inputs Operating Mode Load "1" Load "0" Hold (do nothing) Clk Register Inputs Register Outputs ADDR H L N/C N/C DATAOUT H L N/C N/C
u u u
X
CLKEN
l l h H
ADDR h l X X
DATAIN h l X X
NOTE: 2809 tbl 07 1. H = HIGH voltage level steady state, h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, L =LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, X = Don't care, N/C = No change
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IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V 10%)
IDT7M1024 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage Test Condition VCC = 5.5V, VIN = 0V to VCC Min. -- -- -- 2.4 Max. 40 10 0.4 -- Unit A A V V
2809 tbl 08
CE = VIH, VOUT = 0V to VCC
IOL = 4mA IOH = -4mA
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5V 10%)
IDT7M1024SxxG, IDT7M1024SxxGB -20 Symbol Parameter Dynamic ICC Operating Current (Both Ports Active) Standby ISB1 Current (Both Ports--TTL Level Inputs) Standby ISB2 Current (One Port--TTL Level Inputs) ISB3 Full Standby Current (Both Ports--CMOS Level Inputs) ISB4 Full Standby Current (One Port--CMOS Level Inputs) -25 Typ. -- -- -- -- -- -- -- -- -- -- Max. 1480 1360 680 640 1080 1000 80 80 1040 960 Typ. -- -- -- -- -- -- -- -- -- -- -30 Max. 1440 -- 560 -- 1000 -- 80 -- 960 -- mA mA mA mA Unit mA Test Condition Version Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Typ. Max. -- -- -- -- -- -- -- -- -- -- -- 1440 -- 720 -- 1080 -- 80 -- 1040
CE VIL
Outputs Open f = fMAX(1) L_CE and R_CE VIH f = fMAX(1) L_CE or R_CE VIH Active Port Outputs Open, f = fMAX(1) Both Ports R_CE and L_CE VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V, f = 0(2) One Port L_CE or R_CE VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, Active Port Outputs Open, f = fMAX(1)
NOTES: 2809 tbl 09 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to inputs at CMOS level standby.
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IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1, 2 and 3
2809 drw 03
2909 tbl 10
DATA OUT Zo = 50 50 1.5V
Figure 1. Output Load
5V
8 7
1250
6
DATA OUT 775 5pF*
TAA 5 (Typical, ns) 4
3 2 1
2809 drw 04
Figure 2. Output Load (for tCLZ, tCHZ, tOLZ, and tOHZ) *Including scope and jig.
20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
2809 drw 05
Figure 3. Lumped Capacitive Load, Typical Derating
AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE -- (READ AND WRITE CYCLE TIMING)
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
7M1024SxxG, 7M1024SxxGB -20 Symbol tCLK tCLKH tCLKL tCQV tRSU tRHD tCOH tCLZ tCHZ tOE tOLZ tOHZ tCSU tCHD tCWDD Parameter Clock Cycle Time Clock HIGH Time Clock LOW Time Clock HIGH to Output Valid Registered Signal Set-up Time Registered Signal Hold Time Data Output Hold After Clock HIGH Clock HIGH to Output Low-Z Clock HIGH to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Clock Enable, Disable Set-up Time Clock Enable, Disable Hold Time Write Port Clock HIGH to Read Data Delay Min. Max. 20 8 8 -- 5 2 3 2 2 -- 0 -- 5 3 -- -- -- -- 20 -- -- -- -- 9 10 -- 9 -- -- 35 -25 25 10 10 -- 6 2 3 2 2 -- 0 -- 6 3 -- -- -- -- 25 -- -- -- -- 12 12 -- 11 -- -- 45 30 12 12 -- 7 2 3 2 2 -- 0 -- 7 3 -- -30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2809 tbl 11
Min. Max. Min. Max. -- -- -- 30 -- -- -- -- 15 15 -- 14 -- -- 55
Port-to-Port Delay
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IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE, EITHER SIDE(1,2)
tCLK CLOCK tCLKH tCLKL tCSU tCHD tCSU
CLKEN
tRSU tRHD
CE
R/W
ADDRESS
An tCQV
An + 1 tCOH Qn tCLZ
An + 2
An + 3 tCHZ
DATAOUT
Qn + 1 tOHZ tOLZ tOE
Qn + 1
OE
TIMING WAVEFORM OF READ CYCLE WITH PORT-TO-PORT DELAY
CLOCKR
2809 drw 06
R/WR
ADDRR
MATCH
NO MATCH
DATA INR
VALID
CLOCKL
R/WL
ADDRL
MATCH
NO MATCH
tCWDD DATA OUTL
NOTES: 1. L_CE = R_CE = L, L_CLKEN = R_CLKEN = L 2. OE = L for the reading port.
VALID
tCQV
VALID
tCOH
2809 drw 07
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IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ-TO-WRITE CYCLE No. 1, CE HIGH(1)
tCLK CLOCK tCLKH tCLKL tCLKH tCLK tCLKL
CLKEN
tRSU tRHD
CE
R/W
ADDRESS
An
An + 1
An + 2
An + 3
DATAIN tCQV DATAOUT tCLZ
NOTE: 1. OE LOW throughout.
Dn + 2 tCHZ Qn
Dn + 3
2809 drw 08
TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1, CE LOW(1,2)
tCLK CLOCK tCLKH tCLKL
CLKEN
tRSU tRHD
CE
R/W
ADDRESS
An
An + 1
An + 1
An + 2
DATAIN tCQV DATAOUT tCLZ tCHZ Qn
Dn + 1
Dn + 2
2809 drw 09
NOTES: 1. During dead cycle, if CE is LOW, data will be written into array. 2. OE LOW throughout.
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IDT7M1024 4K x 36 BiCMOS SYNCHRONOUS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
TOP VIEW 1.327 1.353 SIDE VIEW 0.045 0.055 0.015 0.021 1.327 1.353 0.100 TYP 0.195 MAX 0.125 0.135 PIN A1 0.050 TYP
BOTTOM VIEW
2809 drw 10
ORDERING INFORMATION
IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B Ceramic Pin Grid Array
G
20 25 30
Commercial Only Military Only
Speed in Nanoseconds
S
Standard Power
7M1024 4K x 36-Bit Synchronous Dual-Port RAM Module
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